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2.7 v to 5.5 v, <100 a, 14-bit nano dac? d/a in sc70 package preliminary technical data ad5641 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 6-lead sc70 package power-down to <100 na @ 3 v single 14-bit dac: a version: 16 lsb inl micropower operation: max 100 a @ 5 v 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to 0 v with brownout detection 3 power-down functions low power serial interface with schmitt-triggered inputs on-chip output buffer amplifier, rail-to-rail operation sync interrupt facility applications voltage level setting portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5641, a member of the nano dac family, is a single, 14-bit, buffered, voltage out dac that operates from a single 2.7 v to 5.5 v supply, consuming <100 a at 5 v. the part comes in a tiny sc70 package. its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. the ad5641 utilizes a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with spi?, qspi?, microwire?, and dsp interface standards. the reference for ad5641 is derived from the power supply inputs and, therefore, gives the widest dynamic output range. the part incorporates a power-on reset circuit, which ensures that the dac output powers up to 0 v and remains there until a valid write to the device takes place. the ad5641 contains a power-down feature that reduces current consumption to <100 na at 3 v, and provides software- selectable output loads while in power-down mode. the part is put into power-down mode over the serial interface. the low power consumption of the part in normal operation makes it ideally suited to portable battery-operated equipment. the combination of small package and low power makes this nano dac device ideal for level-setting requirements such as generating bias or control voltages in space-constrained and power-sensitive applications. functional block diagram power-on reset dac register 14-bit dac input control logic power-down control logic ad5641 v dd gnd ref(+) resistor network v out sync sclk din output buffer 04611-a-001 figure 1. table 1. related devices part number description ad5601/ad5611/ad5621 2.7 v to 5.5 v, <100 a, 8-/10-/12-bit, nano dac? d/a, spi interface, sc70 package the ad5641 is designed with new technology and comes in a space-saving sc70 package. product highlights 1. available in a space-saving 6-lead sc70 package. 2. low power, single-supply operation. the ad5641 operates from a single 2.7 v to 5.5 v supply and typically consumes 0.2 mw at 3 v and 0.5 mw at 5 v, making it ideal for battery-powered applications. 3. the on-chip output buffer amplifier allows the output of the dac to swing rail-to-rail with a typical slew rate of 0.5 v/s. 4. reference derived from the power supply. 5. high speed serial interface with clock speeds up to 30 mhz. 6. designed for very low power consumption. the interface powers up only during a write cycle. 7. power-down capability. when powered down, the dac typically consumes <100 na at 3 v. 8. power-on reset with brownout detection.
ad5641 preliminary technical data rev. prd | page 2 of 20 table of contents specifications..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions ............................ 6 terminology ...................................................................................... 7 typical performance characteristics ............................................. 8 general description ....................................................................... 12 d/a section................................................................................. 12 resistor string............................................................................. 12 output amplifier........................................................................ 12 serial interface ............................................................................ 12 input shift register .................................................................... 12 sync interrupt .......................................................................... 13 power-on reset.......................................................................... 13 power-down modes .................................................................. 13 microprocessor interfacing....................................................... 13 applications..................................................................................... 15 choosing a reference as power supply for ad5641 ............. 15 bipolar operation using the ad5641 ..................................... 15 using ad5641 with an opto-isolated interface .................... 16 power supply bypassing and grounding................................ 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history revision prd: preliminary version
preliminary technical data ad5641 rev. prd | page 3 of 20 specifications v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments static performance resolution 14 bits relative accuracy 1 16 lsb a grade differential nonlinearity 1 1 lsb guaranteed monotonic by design zero code error +0.0005 mv all 0s loaded to dac register offset error 10 mv full-scale error 0.0004 lsb all 1s loaded to dac register gain error 0.037 % of fsr zero code error drift 5.0 v/c gain temperature coefficient 2.0 ppm of fsr/c output characteristics 2 output voltage range 0 v dd v output voltage settling time 6 10 s code ? to ? slew rate 0.5 v/s capacitive load stability 470 pf r l = 1000 pf rl = 2 k? output noise spectral density 120 nv/hz dac code = midscale, 1 khz noise 2 uv dac code = midscale, 0.1 hz to 10 hz bandwidth digital-to-analog glitch impulse 5 nv-s 1 lsb change around major carry digital feedthrough 0.2 nv-s dc output impedance 1 ohm short-circuit current 20 ma v dd = 3 v/5 v logic inputs input current 1 a v inl , input low voltage 0.8 v v dd = 5 v 0.6 v v dd = 2.7 v v inh , input high voltage 1.8 v v dd = 5 v 1.4 v v dd = 2.7 v pin capacitance 3 pf power requirements v dd 2.7 5.5 v all digital inputs at 0 or v dd i dd (normal mode) dac active and excluding load current v dd = 4.5 v to 5.5 v 100 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 70 a v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.2 1 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 0.05 1 a v ih = v dd and v il = gnd power efficiency i out /i dd tbd % i load = 2 ma and v dd = 5 v 1 linearity calculated using a reduced code range. 2 guaranteed by design and characterization, not production tested.
ad5641 preliminary technical data rev. prd | page 4 of 20 timing characteristics v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. see figure 2. table 3. parameter limit 1 unit test conditions/comments t 1 2 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 12 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 33 ns min minimum sync high time t 9 13 ns min sync rising edge to next sclk fall ignore 1 all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 30 mhz. t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 d2 d14 d15 din sync sclk 04611-a-002 t 9 t 1 t 8 d15 d14 figure 2. timing diagram
preliminary technical data ad5641 rev. prd | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7.0 v digital input voltage to gnd C0.3 v to v dd + 0.3 v v out to gnd C0.3 v to v dd + 0.3 v operating temperature range industrial C40c to +125c storage temperature range C65c to +160c maximum junction temperature 150c sc70 package ja thermal impedance 332c/w jc thermal impedance 120c/w lead temperature, soldering vapor phase (60 s) 215c infrared (15 s) 220c esd 2.0 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitiv e device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefor e, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5641 preliminary technical data rev. prd | page 6 of 20 pin configuration and function descriptions top view (not to scale) v dd gnd sclk din ad5641 v out sync 1 2 3 6 5 4 04611-a-003 figure 3 6-lead sc70 pin configuration table 5. pin function descriptions pin no. mnemonic function 1 sync level-triggered control input (active low). this is the fr ame synchronization signal for the input data. when sync goes low, it enables the input shift register, and data is tr ansferred in on the falling edges of the clocks that follow. the dac is updated following the 16 th clock cycle unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac. 2 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data ca n be transferred at rates up to 30 mhz. 3 din serial data input. this device has a 16-bit shift regi.ster. da ta is clocked into the register on the falling edge of the serial clock input. 4 v dd power supply input. the ad5641 can be operated from 2.7 v to 5.5 v. v dd should be decoupled to gnd. 5 gnd ground reference point for all circuitry on the ad5641. 6 v out analog output voltage from the dac. the ou tput amplifier has rail-to-rail operation.
preliminary technical data ad5641 rev. prd | page 7 of 20 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl versus code plot can be seen in figure 4. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl versus code plot can be seen in figure 7. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5641, because the output of the dac cannot go below 0 v. zero-code error is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. a plot of zero-code error versus temperature can be seen in figure 6. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error versus temperature can be seen in figure 6. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percent of the full-scale range. tota l una djuste d error total unadjusted error (tue) is a measure of the output error taking all the various errors into account. a typical tue versus code plot can be seen in figure 5. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 18. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.
ad5641 preliminary technical data rev. prd | page 8 of 20 typical performance characteristics code 04611-a-004 ?1.5 ?1.0 ?0.5 0 1.0 0.5 1.5 2.0 2.5 0 2k 4k 6k 8k 10k 12k 14k 16k inl error (lsbs) figure 4. typical inl plot 0 2 4 6 8 10 12 14 16 18 256 2k 4k 6k 8k 10k 12k 14k 16k tue (lsbs) code 04611-a-005 figure 5. total unadjusted error figure 6. zero-scale error and full-scale error vs. temperature ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 2k 4k 6k 8k 10k 12k 14k 16k dnl error (lsbs) code 04611-a-007 figure 7. typical dnl plot figure 8. inl and dnl vs. supply figure 9. i dd histogram @ v dd = 3 v/5 v
preliminary technical data ad5641 rev. prd | page 9 of 20 ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 ?15 ?10 ?5 0 5 10 15 i(ma) ? v o (v) 04611-a-010 dac loaded with ff code v dd = 5v t a = 25 c dac loaded with 00 code figure 10. source and sink current capability figure 11. supply current vs. temperature figure 12. full-scale settling time figure 13. supply current vs. code figure 14. supply current vs. supply voltage figure 15. half-scale settling time
ad5641 preliminary technical data rev. prd | page 10 of 20 ch2 ch1 04611-a-016 v dd = 5v t a = 25 c v dd v out = 70mv ch1 1v, ch2, time base = 20 s/div figure 16. power-on reset to 0 v ch1 1v, ch2 5v, time base = 50 s/div ch2 ch1 04611-a-017 v dd v out v dd = 5v t a = 25 c figure 17. v dd vs. v out (power-down) figure 18. digital-to-analog glitch impulse 04611-a-019 ch1 v dd = 5v t a = 25 c midscale loaded ch1 5uv/div figure 19. 1/f noise, 0.1 hz to 10 hz bandwidth ch1 5v, ch2 1v, time base = 5 s/div ch1 ch2 v out clk 04783-c-020 v dd = 5v t a = 25 c figure 20. exiting power-down figure 21. harmonic distortion on digitally generated waveform
preliminary technical data ad5641 rev. prd | page 11 of 20 0 20 40 60 80 100 120 140 0 5 10 15 20 25 frequency (mhz) i dd (ua) 04611-a-023 3/4 scale full scale 1/4 scale midscale zero scale figure 22. i dd vs. sclk vs. code noise spectral density 0 20 40 160 60 80 100 120 140 200 180 1k 10k 100k frequency code 0x2040 zero scale midscale full scale 04611-a-024 nv/ hz figure 23. noise spectral density
ad5641 preliminary technical data rev. prd | page 12 of 20 general description d/a section the ad5641 dac is fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 24 is a block diagram of the dac architecture. v dd v out gnd resistor network ref (+) ref (?) output amplifier dac register 04611-a-025 figure 24. dac architecture because the input coding to the dac is straight binary, the ideal output voltage is given by ? ? ? ? ? ? = 16384 d v v dd out where d is the decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 16,384. resistor string the resistor string section is shown in figure 25. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaran- teed monotonic. r r r r r to output amplifier 04611-a-026 figure 25. resistor string section output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 v to v dd . it is capable of driving a load of 2 k? in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 10. the slew rate is 0.5 v/s, with a half- scale settling time of 8 s with the output unloaded. serial interface the ad5641 has a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 16-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the ad5641compatible with high speed dsps. on the 16 th falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in dac register contents and/or a change in the mode of operation). at this stage, the sync line might be kept low or brought high. in either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 1.8 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part, as mentioned above. however, it must be brought high again just before the next write sequence. input shift register the input shift register is 16 bits wide (see figure 26). the first two bits are control bits that determine the parts mode of operation (normal mode or any one of three power-down modes). for a complete description of the various modes, see the power-down modes section. the next 16 bits are the data bits, which are transferred to the dac register on the 16 th falling edge of sclk. data bits db15 (msb) db0 (lsb) pd1 pd0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 normal operation 1 k ? to gnd 100 k ? to gnd three-state power-down modes 0 0 1 1 0 1 0 1 04611-a-027 figure 26. input register contents
preliminary technical data ad5641 rev. prd | page 13 of 20 04611-a-028 din db15 db16 db0 db0 invalid write sequence: sync high before 16 th falling edge valid write sequence, output updates on the 16 th falling edge sync sclk figure 27. sync interrupt facility sync interrupt in a normal write sequence, the sync line is kept low for at least 16 falling edges of sclk and the dac is updated on the 16 th falling edge. however, if sync is brought high before the 16 th falling edge, this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 27). power-on reset the ad5641 contains a power-on reset circuit that controls the output voltage during power-up. the dac register is filled with zeros and the output voltage is 0 v. it remains there until a valid write sequence is made to the dac. this is useful in applica- tions in which it is important to know the state of the dacs output while it is in the process of powering up. power-down modes the ad5641 have four separate modes of operation. these modes are software-programmable by setting two bits (db15 and db14) in the control register. table 6 shows how the state of the bits corresponds to the mode of operation of the device. table 6. modes of operation for the ad5641 db15 db14 operating mode 0 0 normal operation power-down mode 0 1 1 k? to gnd 1 0 100 k? to gnd 1 1 three-state when both bits are set to 0, the part works normally with its normal power consumption of 100 a maximum at 5 v. however, for the three power-down modes, the supply current falls to <100 na at 3 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options: the output is connected internally to gnd through a 1 k? resistor or a 100 k? resistor, or the output is left open- circuited (three-state). figure 28 shows the output stage. power-down circuitry resistor network v out resistor string dac amplifier 04611-a-029 figure 28. output stage during power-down the bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when the power- down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s for v dd = 3 v. see figure 20 for a plot. microprocessor interfacing ad5641 to adsp-2101/adsp-2103 interface figure 29 shows a serial interface between the ad5641 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set up to operate in sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. adsp-2101/ adsp-2103* ad5641* *additional pins omitted for clairty tfs dt sclk sync din sclk 04611-a-030 figure 29. ad5641 to adsp-2101/adsp-2103 interface
ad5641 preliminary technical data rev. prd | page 14 of 20 ad5641 to 68hc11/68l11 interface figure 30 shows a serial interface between the ad5641 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5641, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be configured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5641, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. 68hc11/ 68l11 ad5641* *additional pins omitted for clairty pc7 sck mosi sync sclk din 04611-a-031 figure 30. ad5641 to 68hc11/68l11 interface ad5641 to blackfin? adsp-bf53x interface figure 31 shows a serial interface between the ad5641 and the blackfin adsp-bf53x microprocessor. the adsp-bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5641, the setup for the interface is as follows: dt0pri drives the sdin pin of the ad5641, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. adsp-bf53x ad5641 *additional pins omitted for clairty dt0pri tsclk0 tfs0 din sclk sync 04611-a-032 figure 31. ad5641 to blackfin adsp-bf53x interface ad5641 to 80c51/80l51 interface figure 32 shows a serial interface between the ad5641 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5641, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmit- ted to the ad5641, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in a format that has the lsb first. the ad5641 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. 80c51/80l51* ad5641* *additional pins omitted for clairty p3.3 txd rxd sync sclk din 04611-a-033 figure 32. ad5641 to 80c51/80l51 interface ad5641 to microwire interface figure 33 shows an interface between the ad5641 and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5641 on the rising edge of the sk. microwire* ad5641* *additional pins omitted for clairty cs sk so sync sclk din 04611-a-034 figure 33. ad5641 to microwire interface
preliminary technical data ad5641 rev. prd | page 15 of 20 applications choosing a reference as power supply for ad5641 the ad5641 comes in a tiny sc70 package with less than a 100 a supply current. because of this, the choice of reference depends on the application requirements. for space-saving applications, the adr425 is available in an sc70 package and has excellent drift at 3 ppm/c. it also provides very good noise performance at 3.4 v p-p in the 0.1 hz to 10 hz range. because the supply current required by the ad5641 is extremely low, it is ideal for low supply applications. the adr293 voltage reference is recommended in this case. this requires 15 a of quiescent current and can, therefore, drive multiple dacs in one system, if required. ad 5641 3-wire serial interface sync sclk din 7v 5v v out = 0v to 5v adr425 04611-a-035 figure 34. adr425 as power supply to ad5641 some recommended precision references for use as supplies to the ad5641 are listed in table 7. table 7. precision references for use with ad5641 part no. initial accuracy (mv max) temperature drift (ppm/c max) 0.1 hz to 10 hz noise (v p-p typ) adr435 6 3 3.4 adr425 6 3 3.4 adr02 5 3 15 adr395 6 25 5 bipolar operation using the ad5641 the ad5641 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 35. the circuit in figure 35 gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = 1 1 2 1 16384 r 2 r v r r r d v v dd dd o where d represents the input code in decimal (0 C 16384). with v dd = 5 v, r1 = r2 = 10 k?: v 5 16384 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v with 0x0000 corre- sponding to a C5 v output, and 0x3fff corresponding to a +5 v output. r2 = 10k 04611-a-036 ? +5v ?5v ad820/ op295 3-wire serial interface +5v ad5641 10 f 0.1 f v dd v out r1 = 10k ? 5v figure 35. bipolar operation with the ad5641
ad5641 preliminary technical data rev. prd | page 16 of 20 using ad5641 with an opto-isolated interface in process-control applications in industrial environments, it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous common- mode voltages that might occur in the area where the dac is functioning. opto-isolators provide isolation in excess of 3 kv. because the ad5641 uses a 3-wire serial logic interface, it requires only three opto-isolators to provide the required isolation (see figure 36). the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5641. v dd 0.1 f v dd v dd 10k ? 10k ? 10k ? +5v regulator v out gnd 04611-a-037 din sync sclk power 10 f v dd sync sclk data ad5641 figure 36. ad5641 with an opto-isolated interface power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5641 should have separate analog and digital sections, each having its own area of the board. if the ad564 1 is in a system where other devices require an agnd to dgnd connection, the connection should be made at one point only. this ground point should be as close to the ad5641 as possible. the power supply to the ad5641 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi), such as in common ceramic types of capaci- tors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals, if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
preliminary technical data ad5641 rev. prd | page 17 of 20 outline dimensions 0.22 0.08 0.46 0.36 0.26 8 4 0 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 4 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 1.30 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203ab figure 37. 6-lead plastic surface mount package [sc70] (ks-6) dimensions shown in millimeters ordering guide model temperature range description package description package option ad5641aks C40c to +125c 16 lsb inl 6-lead plastic surface mount package (sc70) ks-6
ad5641 preliminary technical data rev. prd | page 18 of 20 notes
preliminary technical data ad5641 rev. prd | page 19 of 20 notes
ad5641 preliminary technical data rev. prd | page 20 of 20 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.

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